2006 – Graduated from MIET with master’s degree.
2009 – Defended his Candidate’s thesis on “Research and development of methods for increasing the performance of integrated circuits of multicore microprocessors based on increasing the efficiency of switching logic”.
Since 2004 – Technician, Engineer, Senior Researcher, Head of the Laboratory for Verification of SoC and SF-Blocks, JSC ELVIS.
Since 2016 – Member of the Council for Professional Qualifications in the Nanoindustry.
Developing Advanced Micro- and Nanoelectronic Systems (MES)
- Design and verification of complex functional blocks
Area of scientific interests:
Multi-core systems on a chip (SoC), processors, functional verification, test generation, automation of the development process of IS SoCs, performance analysis of multi-core heterogeneous SoCs.
Author of over 40 scientific papers, including 2 patents for invention.
Web of Science ResearcherID – D-1256-2017