Vertyanov Denis Vasilievich

Brief biography

2007 – Graduated from MIET with bachelor's degree.

2009 – Graduated from MIET with master’s degree, major 210200 “Design and technology of electronic means”.

2009-2012 – Head of the CAD sector of CJSC STC ELINS.

2012 – Graduated from the postgraduate course at MIET, major 05.27.06.

Since 2012 – Senior engineer and assistant, senior lecturer of the Institute of Nano and Microsystem Technology.


  • Topological Design Using Expedition PCB (CAD Mentor Graphics)

  • Fundamentals of automation of engineering tasks in the product data management system

Scientific activity

Research Interests:

  • design and technology of multi-chip modules;

  • technology of flexible and flexible-rigid printed circuit boards;

  • technology of solderless and non-welded installation of electronic components;

  • internal installation of active and passive electronic components;

  • automation of design and technological tasks;

  • product and life cycle data management systems (PDM / PLM systems)

Web of Science ResearcherID – E-2533-2014